1. Field of the Invention
The present invention relates to a sense-amplifier circuitry for driving a solid-state memory device and more particularly, to a circuitry of high-speed current-mode sense-amplifier for using in multi-port SRAM memory device.
2. Description of the Prior Art
The trend in modem microelectronic devices and in the growing market requires low power, high-density devices to minimize device dimension in order to reduce unit cost per function and to improve device performance. In particular the semiconductor memory devices such as DRAM and SRAM are two types of major memories widely using for storing the video and audio data in personal computer. Since a high density and low power consumption of memory devices are demanded, hence, the requirement of virtual contact bit lines that generally be taken make one bit line loaded with several tens of memory cells. Therefore, current following through a addressed memory cell having data "1" or "0" varies of about tens of .mu.A. Furthermore, a very low voltage may be as low as several tenths or hundreds mV is commonly sensed on data bus representing the addressed data. A suitable amplification is typically performed in a sense amplifier 200 to appropriately read the addressed data.
As shown in FIG. 1 is a typical embodiment of sense-amplifier 200 circuitry in accordance with the prior art for using in multi-port RAM or DRAM. The sense-amplifier 200 comprises a current-direction sense-amplifier circuit 300, and a differential amplifier 400. The NMOS transistors M1, M2, M3, M4, M5 and M6 constitute the current-direction sense-amplifier circuit 300. The transistors M1 and M2 are with gates coupled each other for receiving an enable signal to turn on the circuit 300, and with drain terminals coupled for receiving a power V.sub.DD from a power supply. The source terminals of transistors M1 and M2 are connected with the output nodes n1 and n0, respectively. The transistor M3 and M4 are cross coupled by the gate terminals and the drain terminals, respectively, and the drain terminals of transistor M3 and M4 are coupled with the output nodes n0 and n1 respectively. Similar to the transistors M1 and M2, the transistor M5 and M6 are with gates coupled for receiving a voltage V.sub.DD and with source terminal coupled for receiving a voltage reference V.sub.SS. The drain terminals of transistor M5 and M6 are connected with the source terminals of the transistors M3, and M4. In addition, the source of the transistor M3 is connected with an input data node IN for receiving a "data" from a node IN which couples with a single-end bit line.
The current-direction sense-amplifier circuit 300 is in response to a current flow in or flow out from the bit line 100 to generate two differential input potentials, no, and n1 of differential amplifier 400.
The differential amplifier circuit 400 includes two PMOS transistor U7 and U8 which form a current mirror circuit, two NMOS transistor U9 and U10 which receive the output voltages of the current-direction sense-amplifier circuit 300 no and n1, and an NMOS transistor U11 for receiving an enable signal. The differential amplifier 400 is powered by turn on the NMOS transistor U11 with the enable signal.
The operation of the current-direction sense-amplifier circuit 300 is based on the direction of current flow at node IN. When current flow into node IN, the source voltage of the transistor M3 goes up. This results in a decrease in Vgs (the voltage of gate to source) of the transistor M3 and in turn an increase in the source voltage of the transistor M1. Thus the voltage of node n1 (herein and after called V.sub.n1) increases. At the same time, Vgs of the transistor M4 increases, which increases drain current of the transistor M4 and cause a decrease of source voltage of the transistor M2. Thus V.sub.n0 decreases. Since node n0 connects to gate of transistor M3, thus as V.sub.n0 decreases, the Vgs of transistor M3 further increases, and then n1 further goes up. Therefore a positive feedback loop is established. A differential voltage .DELTA.V1 between n1 and n0 appears.
Similarly, when current flows out from IN, the source voltage of transistor M3 goes down. This results in an increase in Vgs of transistor M3, and in turn a decrease in the source voltage of transistor M1. Thus V.sub.n1 decreases. At the same time, the Vgs of the transistor M4 decreases, which causes a decrease of drain current of the transistor M4 and a increase of the source voltage of the transistor M2. Thus V.sub.n0 increases with a result that Vgs of the transistor M3 further decreases. The voltage of n1 further goes down. Once again, a positive feedback loop is established and a differential voltage .DELTA.V2 between node n1 and n0 appears.
However, this positive feedback loop voltage gain is merely approximately close to unity. In addition, the voltage swing at n0 is smaller than that of at node n1. Therefore, when an increase voltage .DELTA.V appears at node IN, an incremental differential voltage .DELTA.V1=V.sub.n1 -Vv.sub.n0. On the other hand, as a decrease .DELTA.V appears at node IN, a decrement differential voltage .DELTA.V2=V.sub.n0 -V.sub.n1, is generated, however, .DELTA.V2&lt;.DELTA.V1. That is, an incremental gain and a decrement loop voltage gain are not uniform.
The simulation results are shown in FIGS. 2-5. In the Figs, the data signal 160 is received from the data input terminal IN, and then two signal 170, and 180 are output form the node n0 and n1, respectively. Then the signals 170, and 180 are input into the differential sense-amplifier 400 to obtain the digital data signal 190 from the OUT terminal. FIG. 2 shows typical variations of .DELTA.V1 and .DELTA.V2 with respect to the input data signal received from the node IN. The maximum of the differential voltages .DELTA.V1.sub.max and .DELTA.V2.sub.max are only about 0.35V and 0.25V, respectively. For achieve the goals of generating symmetrical differential gains, adjusting the channel widths of NMOS transistors in the current sense-amplifier circuit 300 are carried out. However, as shown in FIGS. 3 and 4, the voltage swing in node n0 is small. The larger of voltage swing in n1, results in larger differential voltage .DELTA.V1 and smaller differential voltage .DELTA.V2 is introduced. This output digital signal of sense-amplifier 200, especially while the DATA is "low", a spike-like wave form is formed. On the other hand, the decrement of differential voltage .DELTA.V1 gives the narrow width of digital data output "1", as shown in FIG. 5. All attempts by adjusting the sizes of transistor to increase the voltage swing of n0 are ineffectual. Small loop voltage gain (e.g. &lt;0.2 V differential voltage) and asymmetrical loop voltage gain may cause circuit to risk process variation and noise interference. Thus there is an invention in need to increase loop voltage gain and to produce symmetrical loop voltage gain.